https://doi.org/10.1051/epjconf/201612700017
FPGA-Based Approach to Level-1 Track Finding at CMS for the HL-LHC
Cornell University, Ithaca, NY, USA
a e-mail: louise.skinnari@cern.ch
Published online: 15 November 2016
The high luminosity upgrade of the LHC is expected to deliver luminosities of 7.5 × 1034 cm−2s−1, with an average of 140–200 overlapping proton-proton collisions in each bunch crossing at a frequency of 40 MHz. To maintain manageable trigger rates under these conditions track reconstruction will be incorporated in the all-hardware first level of the CMS trigger. A track-finding algorithm based on seed tracklets has been developed and implemented on commercially available FPGAs for this purpose. An overview of the algorithm is presented, results are shown of its expected performance from simulations, and an implementation of the algorithm in a Xilinx Virtex-7 FPGA for a hardware demonstrator system is discussed.
© The Authors, published by EDP Sciences, 2016
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
