Gate recess study for high thermal stability pHEMT devices
School of Microelectronic Engineering, Pauh Putra Campus, University Malaysia Perlis (UniMAP), 02600 Arau, Perlis, MALAYSIA
2 School of Electrical and Electronic Engineering, University of Manchester, M13 9PL, UK
* Corresponding author: firstname.lastname@example.org
Published online: 22 November 2017
Gate formation is a crucial steps, especially in FET fabrication process. At this steps, the characteristics are very much influenced by the processing parameters, particularly in the processing temperature. In this paper, we report the thermal stability study and sidewall etch to reduce the off-state Schottky’s gate leakage on 1 μm gate pHEMT device. In our study, we found that low sintering temperatures of 200°C is preferable and sidewall etching of 10 minutes has reduces the gate leakage by almost 5 times as compared with the devices with no sidewall etching. The optimised processing recipe is proposed for low off-state Schottky’s gate leakage, where low leakage has significant influence in the device performances, especially for future high speed and low noise applications.
© The Authors, published by EDP Sciences, 2017
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. (http://creativecommons.org/licenses/by/4.0/).