https://doi.org/10.1051/epjconf/202532103002
Buried power rails and backside power distribution for nanometer-scale IC design
National Research University of Electronic Technology (MIET), Bld. 1, Shokin Square, Zelenograd, Moscow, Russia
* Corresponding author: darrrlight@gmail.com
Published online: 10 March 2025
The technologies of buried power rails and backside power distribution networks are promising tools for reducing the size of nanoscale CMOS-based circuits. They provide significant improvement in many system-level parameters, for example, voltage drop and power losses are reduced by more than 2 times, and when using a ruthenium buried power rail - by more than 4 times, while also significantly reducing the delay on critical paths and the overall circuit area. However, to fully realize the potential of this technology, it is necessary to solve a number of problems related to the technological process and architecture. In this paper, the authors examine the prospects and challenges associated with the implementation of buried power rail technology and backside power distribution networks. Physical characteristics of semiconductor devices were also selected for model creation and technological simulation in the Synopsys Sentaurus TCAD environment, as well as for physical synthesis in commercial computer-aided design systems and open-source software. The developed models and methods will be included in the open design flow for integrated CMOS circuits with a technological process of 15 nm and below.
© The Authors, published by EDP Sciences, 2025
This is an Open Access article distributed under the terms of the Creative Commons Attribution License 4.0, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
